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» Arithmetic Coding for Low Power Embedded System Design
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ICCD
2004
IEEE
111views Hardware» more  ICCD 2004»
14 years 4 months ago
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Du...
CASES
2006
ACM
14 years 1 months ago
Code transformation strategies for extensible embedded processors
Embedded application requirements, including high performance, low power consumption and fast time to market, are uncommon in the broader domain of general purpose applications. I...
Paolo Bonzini, Laura Pozzi
DAC
2004
ACM
14 years 8 months ago
Multi-profile based code compression
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
Eduardo Wanderley Netto, Rodolfo Azevedo, Paulo Ce...
CASES
2000
ACM
14 years 2 days ago
A first-step towards an architecture tuning methodology for low power
We describe an automated environment to assist a system-on-achip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, an...
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. L...
CODES
2009
IEEE
14 years 2 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles