Sciweavers

314 search results - page 29 / 63
» Arithmetic Coding for Low Power Embedded System Design
Sort
View
IWSOC
2003
IEEE
97views Hardware» more  IWSOC 2003»
14 years 1 months ago
Evaluating Template-Based Instruction Compression on Transport Triggered Architectures
In embedded systems, memory is one of the most expensive resources. Due to this, program code size has turned out to be one of the most critical design constraints. Code compressi...
Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
14 years 3 days ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ARITH
2009
IEEE
14 years 2 months ago
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
Ghassem Jaberipur, Behrooz Parhami
CODES
2010
IEEE
13 years 5 months ago
Accurate online power estimation and automatic battery behavior based power model generation for smartphones
This paper describes PowerBooter, an automated power model construction technique that uses built-in battery voltage sensors and knowledge of battery discharge behavior to monitor...
Lide Zhang, Birjodh Tiwana, Zhiyun Qian, Zhaoguang...
MOBIQUITOUS
2007
IEEE
14 years 2 months ago
Battery-Aware Embedded GPS Receiver Node
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
Dejan Raskovic, David Giessel