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» Array SSA Form and Its Use in Parallelization
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ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 4 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
IPPS
2008
IEEE
14 years 1 months ago
An adaptive parallel pipeline pattern for grids
This paper introduces an adaptive parallel pipeline pattern which follows the GRASP (Grid-Adaptive Structured Parallelism) methodology. GRASP is a generic methodology to incorpora...
Horacio González-Vélez, Murray Cole
AIPR
2003
IEEE
14 years 23 days ago
Stereo Mosaics with Slanting Parallel Projections from Many Cameras or a Moving Camera
This paper presents an approach of fusing images from many video cameras or a moving video camera with external orientation data (e.g. GPS and INS data) into a few mosaiced images...
Zhigang Zhu
TPDS
1998
157views more  TPDS 1998»
13 years 7 months ago
A Compiler Optimization Algorithm for Shared-Memory Multiprocessors
This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, sharedmemory multiprocessors. The algorithm considers data locality, parall...
Kathryn S. McKinley
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
14 years 1 months ago
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
Rafal Karakiewicz, Roman Genov