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ERSA
2010
199views Hardware» more  ERSA 2010»
13 years 8 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
EUROGP
2009
Springer
105views Optimization» more  EUROGP 2009»
14 years 3 months ago
Quantum Circuit Synthesis with Adaptive Parameters Control
The contribution presented herein proposes an adaptive genetic algorithm applied to quantum logic circuit synthesis that, dynamically adjusts its control parameters. The adaptation...
Cristian Ruican, Mihai Udrescu, Lucian Prodan, Mir...
IPPS
2000
IEEE
14 years 2 months ago
Performance of On-Chip Multiprocessors for Vision Tasks
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Vi...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 4 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ISPDC
2010
IEEE
13 years 8 months ago
Pretty Good Accuracy in Matrix Multiplication with GPUs
—With systems such as Road Runner, there is a trend in super computing to offload parallel tasks to special purpose co-processors, composed of many relatively simple scalar proc...
Matthew Badin, Lubomir Bic, Michael B. Dillencourt...