Sciweavers

176 search results - page 21 / 36
» Arrays and References
Sort
View
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
13 years 11 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
CIKM
2009
Springer
13 years 11 months ago
Blog cascade affinity: analysis and prediction
Information propagation within the blogosphere is of much importance in implementing policies, marketing research, launching new products, and other applications. In this paper, w...
Hui Li, Sourav S. Bhowmick, Aixin Sun
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
13 years 11 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
IJKL
2008
106views more  IJKL 2008»
13 years 7 months ago
Activity- and taxonomy-based knowledge representation framework
: Elaborations of Competence-based Knowledge Space Theory (CbKST) incorporate skills that refer to the conceptual information of the domain as well as to the activities learners ar...
Birgit Marte, Christina M. Steiner, Jürgen He...
RTAS
1996
IEEE
13 years 11 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha