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VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 5 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
ICSE
2008
IEEE-ACM
16 years 4 months ago
Creating a cognitive metric of programming task difficulty
Conducting controlled experiments about programming activities often requires the use of multiple tasks of similar difficulty. In previously reported work about a controlled exper...
Brian de Alwis, Gail C. Murphy, Shawn Minto
FASE
2010
Springer
15 years 11 months ago
Analyzing the Impact of Change in Multi-threaded Programs
We introduce a technique for debugging multi-threaded C programs and analyzing the impact of source code changes, and its implementation in the prototype tool Direct. Our approach ...
Krishnendu Chatterjee, Luca de Alfaro, Vishwanath ...
ISCA
2008
IEEE
109views Hardware» more  ISCA 2008»
15 years 11 months ago
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and...
Shimin Chen, Michael Kozuch, Theodoros Strigkos, B...
CCECE
2006
IEEE
15 years 10 months ago
A Formal CSP Framework for Message-Passing HPC Programming
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
John D. Carter, William B. Gardner