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APSEC
2009
IEEE
15 years 2 months ago
A Formal Framework to Integrate Timed Security Rules within a TEFSM-Based System Specification
Abstract--Formal methods are very useful in software industry and are becoming of paramount importance in practical engineering techniques. They involve the design and the modeling...
Wissam Mallouli, Amel Mammar, Ana R. Cavalli
TSE
2010
125views more  TSE 2010»
15 years 2 months ago
Engineering a Sound Assertion Semantics for the Verifying Compiler
—The Verifying Compiler (VC) project is a core component of the Dependable Systems Evolution Grand Challenge. The VC offers the promise of automatically proving that a program or...
Patrice Chalin
APSEC
2008
IEEE
15 years 6 months ago
A Verification Framework for FBD Based Software in Nuclear Power Plants
Formal verification of Function Block Diagram (FBD) based software is an essential task when replacing traditional relay-based analog system with PLC-based software in nuclear rea...
Junbeom Yoo, Sung Deok Cha, Eunkyoung Jee
RE
2010
Springer
14 years 11 months ago
A UML-based static verification framework for security
Secure software engineering is a new research area that has been proposed to address security issues during the development of software systems. This new area of research advocates...
Igor Siveroni, Andrea Zisman, George Spanoudakis
CODES
1998
IEEE
15 years 8 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...