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» Assessing Instructional Technology
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ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 2 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
14 years 1 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
ICS
1989
Tsinghua U.
14 years 1 months ago
Control flow optimization for supercomputer scalar processing
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...
Pohua P. Chang, Wen-mei W. Hwu
WSC
2007
13 years 11 months ago
High-performance computing enables simulations to transform education
This paper presents the case that education in the 21st Century can only measure up to national needs if technologies developed in the simulation community, further enhanced by th...
Dan M. Davis, Thomas D. Gottschalk, Laurel K. Davi...
JMM2
2007
131views more  JMM2 2007»
13 years 9 months ago
Effect of Digital Games on Children's Cognitive Achievement
—Technologies’ rapid advance in developing digital media has been extensively applied in contemporary play materials to enrich children’s play, such as electronic or computer...
Tsung-Yen Chuang, Wei-Fan Chen