100 search results - page 12 / 20 » Associative Memory with Dynamic Synapses |
CSREAESA
2009
13 years 10 months ago
2009
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
PDPTA
2007
13 years 11 months ago
2007
- Multi-core chips present a new computing environment that can benefit from software support for non-numerical applications. Heterogeneous cores will allow efficient sophisticated...
TC
2008
13 years 9 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
ICCD
2003
IEEE
14 years 6 months ago
2003
IEEE
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
EUROPAR
2010
Springer
13 years 9 months ago
2010
Springer
Today, it is possible to associate multiple CPUs and multiple GPUs in a single shared memory architecture. Using these resources efficiently in a seamless way is a challenging issu...