Virtual Page Tag Reduction for Low-power TLBs

We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufficient to perform physical address translation is efficiently identified and used when performing TLB lookups, delivering significant power reductions. Information regarding the virtual address space of the program code and data provided by the compiler is augmented with information regarding the dynamically linked libraries and data allocated run-time by the loader, the dynamic linker, and the memory manager. The hardware support needed is constrained to disabling bitlines of the tag arrays associated to the I-TLB and the D-TLB. Algorithms for identifying the reduced VPNs for power optimized TLB operations together with the required OS support are presented.

• Type: Conference
• Year: 2003
• Where: ICCD
• Authors: Peter Petrov, Alex Orailoglu
• Keywords: Hardware, ICCD 2003, Physical Address Translation, Power Optimized Tlb, Virtual Address Space