103 search results - page 7 / 21 » Asymmetric Memory Fences: Optimizing Both Performance and Im... |
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ICS
2009
Tsinghua U.
14 years 4 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
IPPS
2002
IEEE
14 years 2 months ago
2002
IEEE
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
ASPLOS
1991
ACM
14 years 1 months ago
1991
ACM
Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kern...
DASFAA
2006
IEEE
14 years 1 months ago
2006
IEEE
Sensor networks are multi-hop wireless networks of resource constrained sensor nodes used to realize high-level collaborative sensing tasks. To query and access data generated and ...