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» Asynchronous Data-Driven Circuit Synthesis
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ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
13 years 8 months ago
Teak: A Token-Flow Implementation for the Balsa Language
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
ASPDAC
2001
ACM
127views Hardware» more  ASPDAC 2001»
14 years 2 months ago
High-level design for asynchronous logic
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
Ross Smith, Michiel M. Ligthart
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
14 years 3 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
14 years 11 months ago
Design of Asynchronous Controllers with Delay Insensitive Interface
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
Hiroshi Saito, Alex Kondratyev, Takashi Nanya
ACSD
2005
IEEE
144views Hardware» more  ACSD 2005»
14 years 4 months ago
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...