This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
Alexander B. Smirnov, Alexander Taubin, Ming Su, M...