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» Asynchronous circuit design on reconfigurable devices
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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 26 days ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
14 years 27 days ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett
FPL
2006
Springer
140views Hardware» more  FPL 2006»
13 years 11 months ago
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications
Given large circuit sizes, high clock frequencies, and possibly extreme operating environments, Field Programmable Gate Arrays (FPGAs) are capable of heating beyond their designed...
Phillip H. Jones, John W. Lockwood, Young H. Cho
FPL
2000
Springer
124views Hardware» more  FPL 2000»
13 years 11 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
ISMVL
2000
IEEE
121views Hardware» more  ISMVL 2000»
13 years 12 months ago
Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments o...
Adrian Stoica