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DAC
2004
ACM
14 years 11 months ago
Reducing clock skew variability via cross links
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
DAC
2005
ACM
14 years 11 months ago
Simulation based deadlock analysis for system level designs
In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...
DAC
2005
ACM
14 years 11 months ago
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
King Ho Tam, Lei He
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 7 months ago
A Two-Layer Bus Routing Algorithm for High-Speed Boards
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...
Muhammet Mustafa Ozdal, Martin D. F. Wong
SOFSEM
2010
Springer
14 years 7 months ago
Source Code Rejuvenation Is Not Refactoring
Programmers rely on programming idioms, design patterns, and workaround techniques to make up for missing programming language support. Evolving languages often address frequently ...
Peter Pirkelbauer, Damian Dechev, Bjarne Stroustru...