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» Automated Logical Verification Based on Trace Abstractions
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ASM
2010
ASM
13 years 11 months ago
Automatic Verification for a Class of Proof Obligations with SMT-Solvers
Abstract. Software development in B and Event-B generates proof obligations that have to be discharged using theorem provers. The cost of such developments therefore depends direct...
David Déharbe
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 14 days ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
ICALP
2000
Springer
14 years 10 days ago
Decidable First-Order Transition Logics for PA-Processes
We show the decidability of model checking PA-processes against several first-order logics based upon the reachability predicate. The main tool for this result is the recognizabil...
Denis Lugiez, Ph. Schnoebelen
RTS
2008
131views more  RTS 2008»
13 years 8 months ago
Formal verification of multitasking applications based on timed automata model
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
Libor Waszniowski, Zdenek Hanzálek
CADE
2008
Springer
14 years 9 months ago
Exploring Model-Based Development for the Verification of Real-Time Java Code
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
Niusha Hakimipour, Paul A. Strooper, Roger Duke