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» Automated Logical Verification Based on Trace Abstractions
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DATE
2006
IEEE
117views Hardware» more  DATE 2006»
14 years 2 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
IJAIT
2006
106views more  IJAIT 2006»
13 years 8 months ago
An Empirical Evaluation of Automated Theorem Provers in Software Certification
We describe a system for the automated certification of safety properties of NASA software. The system uses Hoare-style program verification technology to generate proof obligatio...
Ewen Denney, Bernd Fischer 0002, Johann Schumann
ICLP
1995
Springer
14 years 8 days ago
Variants of the Event Calculus
Abstract. The Event Calculus is a narrative based formalism for reasoning about actions and change originally proposed in logic programming form by Kowalski and Sergot. In this pap...
Fariba Sadri, Robert A. Kowalski
ISSTA
2010
ACM
13 years 10 months ago
Analysis of invariants for efficient bounded verification
SAT-based bounded verification of annotated code consists of translating the code together with the annotations to a propositional formula, and analyzing the formula for specifica...
Juan P. Galeotti, Nicolás Rosner, Carlos L&...
KBSE
2008
IEEE
14 years 3 months ago
Inferring Finite-State Models with Temporal Constraints
Finite state machine-based abstractions of software behaviour are popular because they can be used as the basis for a wide range of (semi-) automated verification and validation ...
Neil Walkinshaw, Kirill Bogdanov