444 search results - page 46 / 89 » Automated Logical Verification Based on Trace Abstractions |
ASYNC
1999
IEEE
14 years 20 hour ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
ECSQARU
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. This paper presents a method which allows for merging beliefs expressed thanks to logic programming with stable model semantics. This method is based on the syntactic mer...
CL
2000
Springer
14 years 1 days ago
2000
Springer
Abstract. In this paper a semantic approach for the specification and the management of databases with evolving schemata is introduced. It is shown how a general object-oriented m...
CADE
2006
Springer
14 years 8 months ago
2006
Springer
Abstract. We present a formally verified quantifier elimination procedure for the first order theory over linear mixed real-integer arithmetics in higher-order logic based on a wor...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...