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DATE
2010
IEEE
129views Hardware» more  DATE 2010»
14 years 2 months ago
Block-level bayesian diagnosis of analogue electronic circuits
—Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue...
Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, Han...
ITNG
2010
IEEE
14 years 2 months ago
BAUT: A Bayesian Driven Tutoring System
—This paper presents the design of BAUT, a tutoring system that explores statistical approach for providing instant project failure analysis. Driven by a Bayesian Network (BN) in...
Song Tan, Kai Qian, Xiang Fu, Prabir Bhattacharya
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
14 years 2 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
ICSE
2001
IEEE-ACM
14 years 1 months ago
Case Study: Extreme Programming in a University Environment
Extreme Programming (XP) is a new and controversial sojiware processfor small teams. A practical training courseat the universityof Karlsruheled to thefollowing observations about...
Matthias M. Müller, Walter F. Tichy
ISSTA
1993
ACM
14 years 1 months ago
Mutation Analysis Using Mutant Schemata
Mutation analysis is a powerful technique for assessing and improving the quality of test data used to unit test software. Unfortunately, current automated mutation analysis syste...
Roland H. Untch, A. Jefferson Offutt, Mary Jean Ha...