We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
A simple method is presented to reduce within-group inter-subject scatter in diffusion tensor magnetic resonance imaging (DT-MRI). By "borrowing strength" across co-regi...
Previous CASC competitions have focused on proving difficult problems on small numbers of axioms. However, typical reasoning applications for expert systems rely on knowledge base...
Adam Pease, Geoff Sutcliffe, Nick Siegel, Steven T...