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» Automated Modeling of Custom Digital Circuits for Test
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CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISBI
2006
IEEE
14 years 8 months ago
A diffusion tensor imaging tractography algorithm based on Navier-Stokes fluid mechanics
We introduce a method for estimating regional connectivity in diffusion tensor magnetic resonance imaging (DT-MRI) based on a fluid mechanics model. We customize the Navier-Stokes...
Nathan S. Hageman, David W. Shattuck, Katherine Na...
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
GIS
2003
ACM
14 years 8 months ago
Constructing a dem from grid-based data by computing intermediate contours
We present a technique for creating a digital elevation model (DEM) from grid-based contour data. The method computes new, intermediate contours in between existing isolines. Thes...
Michael B. Gousie, Wm. Randolph Franklin
SIGSOFT
2010
ACM
13 years 5 months ago
Finding latent performance bugs in systems implementations
Robust distributed systems commonly employ high-level recovery mechanisms enabling the system to recover from a wide variety of problematic environmental conditions such as node f...
Charles Edwin Killian, Karthik Nagaraj, Salman Per...