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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 10 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
DAC
2002
ACM
14 years 9 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
ICASSP
2011
IEEE
12 years 11 months ago
Least squares approximation and polyphase decomposition for pipelining recursive filters
Current techniques used in pipelining recursive filters require significant hardware complexity. These techniques attempt to preserve the exact frequency response of the origina...
Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag
DAC
2009
ACM
14 years 9 months ago
Speculation in elastic systems
Speculation is a well-known technique for increasing parallelism of the microprocessor pipelines and hence their performance. While implementing speculation in modern design pract...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...