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JUCS
2010
143views more  JUCS 2010»
13 years 8 months ago
Design of Arbiters and Allocators Based on Multi-Terminal BDDs
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
Václav Dvorák, Petr Mikusek
CODES
2002
IEEE
14 years 2 months ago
Design of multi-tasking coprocessor control for Eclipse
Eclipse defines a heterogeneous multiprocessor architecture template for data-dependent stream processing. Intended as a scalable and flexible subsystem of forthcoming media-proce...
Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
14 years 1 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
ICCD
2005
IEEE
224views Hardware» more  ICCD 2005»
14 years 6 months ago
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware
In this paper we present algorithmic and architectural methodology for building Particle Filters in hardware. Particle filtering is a new paradigm for filtering in presence of n...
Aswin C. Sankaranarayanan, Rama Chellappa, Ankur S...
SOCC
2008
IEEE
233views Education» more  SOCC 2008»
14 years 4 months ago
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards
Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapa...
Yang Sun, Joseph R. Cavallaro