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CASES
2004
ACM
14 years 1 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder
ASYNC
2002
IEEE
124views Hardware» more  ASYNC 2002»
14 years 28 days ago
Synchronous Interlocked Pipelines
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Pe...
BMCBI
2007
108views more  BMCBI 2007»
13 years 8 months ago
Design and implementation of a generalized laboratory data model
Background: Investigators in the biological sciences continue to exploit laboratory automation methods and have dramatically increased the rates at which they can generate data. I...
Michael C. Wendl, Scott Smith, Craig S. Pohl, Davi...
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
14 years 11 days ago
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...
Montek Singh, Steven M. Nowick
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
14 years 2 days ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain