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    ASAP
    2006
    IEEE
    130views Hardware» more  ASAP 2006»
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
    14 years 2 months ago
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
    Download  www.ivgroup.ee.ucla.edu
    Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
    Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
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    ICIP
    2007
    IEEE
    155views Image Processing» more  ICIP 2007»
    Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range
    14 years 2 months ago
    Software Pipelines Design for Variable Block-Size Motion Estimation with Large Search Range
    Download  www.jdl.ac.cn
    This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
    Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao
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    BMCBI
    2010
    94views more  BMCBI 2010»
    A high-throughput pipeline for the design of real-time PCR signatures
    13 years 8 months ago
    A high-throughput pipeline for the design of real-time PCR signatures
    Download  www.bhsai.org
    Background: Pathogen diagnostic assays based on polymerase chain reaction (PCR) technology provide high sensitivity and specificity. However, the design of these diagnostic assays...
    Ravi Vijaya Satya, Kamal Kumar, Nela Zavaljevski, ...
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    IPPS
    2006
    IEEE
    122views Distributed And Parallel Com...» more  IPPS 2006»
    Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
    14 years 2 months ago
    Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
    Download  www.cecs.uci.edu
    Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
    Maryam Mizani, Daler N. Rakhmatov
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    GLVLSI
    2003
    IEEE
    152views VLSI» more  GLVLSI 2003»
    Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
    14 years 1 months ago
    Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
    Download  www.imd.uni-rostock.de
    The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
    Frank Grassert, Dirk Timmermann
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