4359 search results - page 48 / 872 » Automated Pipeline Design |
ISCAS
2002
IEEE
14 years 29 days ago
2002
IEEE
A time-shifted correlated double sampling (CDS) technique is used to compensate for the finite opamp dc gain in the context of a pipelined analog-to-digital converter (ADC). This...
SBCCI
2009
ACM
14 years 2 months ago
2009
ACM
The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for opht...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
GLVLSI
2007
IEEE
13 years 12 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
CCECE
2011
IEEE
12 years 8 months ago
2011
IEEE
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...