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ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
14 years 5 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
DAMON
2007
Springer
14 years 2 months ago
Pipelined hash-join on multithreaded architectures
Multi-core and multithreaded processors present both opportunities and challenges in the design of database query processing algorithms. Previous work has shown the potential for ...
Philip Garcia, Henry F. Korth
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
14 years 11 days ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun
ERSA
2004
148views Hardware» more  ERSA 2004»
13 years 9 months ago
Efficient Floating-point Based Block LU Decomposition on FPGAs
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sr...
CATA
2010
13 years 8 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad