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ITC
2000
IEEE
124views Hardware» more  ITC 2000»
14 years 1 days ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
ASYNC
1998
IEEE
100views Hardware» more  ASYNC 1998»
13 years 12 months ago
An Implicit Method for Hazard-Free Two-Level Logic Minimization
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
Michael Theobald, Steven M. Nowick
KDD
2007
ACM
177views Data Mining» more  KDD 2007»
14 years 8 months ago
Mining optimal decision trees from itemset lattices
We present DL8, an exact algorithm for finding a decision tree that optimizes a ranking function under size, depth, accuracy and leaf constraints. Because the discovery of optimal...
Élisa Fromont, Siegfried Nijssen
CGO
2007
IEEE
14 years 2 months ago
Microarchitecture Sensitive Empirical Models for Compiler Optimizations
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program perform...
Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. S...
ECAI
2004
Springer
14 years 1 months ago
IPSS: A Hybrid Reasoner for Planning and Scheduling
In this paper we describe IPSS (Integrated Planning and Scheduling System), a domain independent solver that integrates an AI heuristic planner, that synthesizes courses of actions...
María Dolores Rodríguez-Moreno, Ange...