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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 1 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
LPAR
2010
Springer
13 years 5 months ago
Synthesis of Trigger Properties
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...
Orna Kupferman, Moshe Y. Vardi