125 search results - page 15 / 25 » Automated Test Set Generation for Statecharts |
DAC
2009
ACM
14 years 8 months ago
2009
ACM
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
DATE
2000
IEEE
14 years 5 days ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
ASE
2005
13 years 7 months ago
2005
Deductive program synthesis systems based on automated theorem proving offer the promise of software that is correct by construction. However, the difficulty encountered in constru...
EWSPT
2003
Springer
14 years 29 days ago
2003
Springer
We present a new approach for the management and enactment of deployment process by a deployment processor ORYA (Open enviRonment to deploY Applications). ORYA aims to integrate te...