67 search results - page 13 / 14 » Automated transistor sizing for FPGA architecture exploratio... |
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...