1240 search results - page 143 / 248 » Automatic 3D Modelling of Architecture |
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
SBACPAD
2005
IEEE
14 years 2 months ago
2005
IEEE
The Data-Flow Graph (DFG) of a parallel application is frequently used to take scheduling decisions, based on the information that it models (dependencies among the tasks and volu...
WETICE
2003
IEEE
14 years 2 months ago
2003
IEEE
The coordination of concurrent activities in collaborative environments is a very important and difficult task. Many approaches for the construction of large-scale flexible grou...
DAC
1995
ACM
14 years 17 days ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
SIGGRAPH
1991
ACM
14 years 15 days ago
1991
ACM
The number of polygons comprising interesting architectural models is many more than can be rendered at interactive frame rates. However, due to occlusion by opaque surfaces (e.g....