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RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
14 years 4 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
14 years 4 months ago
A novel approach to entirely integrate Virtual Test into test development flow
– In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to ...
Ping Lu, Daniel Glaser, Gürkan Uygur, Klaus H...
WWW
2004
ACM
14 years 10 months ago
Converting UML to OWL ontologies
This paper presents automatic generation of the Web Ontology Language (OWL) from an UML model. The solution is based on an MDA-defined architecture for ontology development and th...
Dragan Gasevic, Dragan Djuric, Vladan Devedzic, Vi...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 3 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...
DAC
2009
ACM
14 years 10 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...