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DAC
2008
ACM
14 years 11 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
Aaron P. Hurst
CSE
2009
IEEE
14 years 5 months ago
Ambulation: A Tool for Monitoring Mobility Patterns over Time Using Mobile Phones
An important tool for evaluating the health of patients who suffer from mobility-affecting chronic diseases such as MS, Parkinson’s, and Muscular Dystrophy is assessment of how ...
Jason Ryder, Brent Longstaff, Sasank Reddy, Debora...
EWSN
2006
Springer
14 years 10 months ago
Results of Bit Error Measurements with Sensor Nodes and Casuistic Consequences for Design of Energy-Efficient Error Control Sche
For the proper design of energy-efficient error control schemes some insight into channel error patterns is needed. This paper presents bit error and packet loss measurements taken...
Andreas Willig, Robert Mitschke
ITC
1992
IEEE
76views Hardware» more  ITC 1992»
14 years 2 months ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
ECCV
2004
Springer
14 years 3 months ago
Hand Pose Estimation Using Hierarchical Detection
This paper presents an analysis of the design of classifiers for use in a hierarchical object recognition approach. In this approach, a cascade of classifiers is arranged in a tr...
Bjoern Stenger, Arasanathan Thayananthan, Philip H...