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DASIP
2010
13 years 2 months ago
Hardware code generation from dataflow programs
The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software archi...
Nicolas Siret, Matthieu Wipliez, Jean-Franç...
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 11 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
DATE
2002
IEEE
146views Hardware» more  DATE 2002»
14 years 15 days ago
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, A...
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
14 years 2 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab
EH
2004
IEEE
102views Hardware» more  EH 2004»
13 years 11 months ago
Design Space Issues for Intrinsic Evolvable Hardware
This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of ...
James Hereford, David A. Gwaltney