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152
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CODES
2006
IEEE
15 years 9 months ago
A formal approach to robustness maximization of complex heterogeneous embedded systems
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...
Arne Hamann, Razvan Racu, Rolf Ernst
151
Voted
PRDC
2000
IEEE
15 years 8 months ago
Enforcing synchronous system properties on top of timed systems
A synchronous system model is a simple yet powerful distributed system model that reduces the complexity of the design and implementation of dependable distributed applications. H...
Christof Fetzer
122
Voted
DDECS
2008
IEEE
97views Hardware» more  DDECS 2008»
15 years 10 months ago
Incremental SAT Instance Generation for SAT-based ATPG
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...
Daniel Tille, Rolf Drechsler
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 5 months ago
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumptio
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...
Hua Tang, Ying Wei, Alex Doboli
128
Voted
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...