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ICSE
2004
IEEE-ACM
16 years 4 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
365
Voted
DAC
2012
ACM
13 years 6 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 9 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
118
Voted
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
16 years 26 days ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
ICWE
2005
Springer
15 years 9 months ago
The Role of Visual Tools in a Web Application Design and Verification Framework: A Visual Notation for LTL Formulae
As the Web becomes a platform for implementing complex B2C and B2B applications, there is a need to extend Web conceptual modeling to process-centric applications. In this context,...
Marco Brambilla, Alin Deutsch, Liying Sui, Victor ...