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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 7 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
MIR
2006
ACM
200views Multimedia» more  MIR 2006»
15 years 10 months ago
An adaptive graph model for automatic image annotation
Automatic keyword annotation is a promising solution to enable more effective image search by using keywords. In this paper, we propose a novel automatic image annotation method b...
Jing Liu, Mingjing Li, Wei-Ying Ma, Qingshan Liu, ...
ECBS
2005
IEEE
126views Hardware» more  ECBS 2005»
15 years 9 months ago
Toward Introducing Notification Technology into Distributed Project Teams
Software development can be thought of as the evolution act requirements into a concrete software system. The evolution, achieved through a successive series of elaborations and r...
Jamie L. Smith, Shawn A. Bohner, D. Scott McCricka...
CIDR
2007
208views Algorithms» more  CIDR 2007»
15 years 5 months ago
Impliance: A Next Generation Information Management Appliance
Though database technology has been remarkably successful in building a large market and adapting to the changes of the last three decades, its impact on the broader market of inf...
Bishwaranjan Bhattacharjee, Joseph S. Glider, Rich...
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 9 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...