— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Hybrid automatic repeat-request (HARQ) is critical to an IEEE 802.16e OFDMA network, as it can significantly improve the reliability of wireless link. However, as revealed by our...
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
In this paper, we introduce the design of a Personalized Education (PE) search approach that employs multiple ontologies to automatically generate queries for educational resource...