High-level synthesis using computation-unit integrated memories

Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). In this paper, we propose an architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus...

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
• Keywords: Computation-unit Integrated Memory, Enhanced Memory Subsystem, Hardware, ICCAD 2004, Memory Subsystem