1888 search results - page 6 / 378 » Automatic Implementation of Distributed Systems Formal Speci... |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
EMSOFT
2008
Springer
13 years 9 months ago
2008
Springer
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
EDOC
2005
IEEE
14 years 1 months ago
2005
IEEE
ECOOPW
2000
Springer
13 years 11 months ago
2000
Springer
TCAD
2008
13 years 7 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...