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» Automatic On-chip Memory Minimization for Data Reuse
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PLDI
2004
ACM
14 years 25 days ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
14 years 11 days ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...
INTERSPEECH
2010
13 years 2 months ago
Data pruning for template-based automatic speech recognition
In this paper we describe and analyze a data pruning method in combination with template-based automatic speech recognition. We demonstrate the positive effects of polishing the t...
Dino Seppi, Dirk Van Compernolle
EMSOFT
2005
Springer
14 years 28 days ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
14 years 1 months ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...