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CF
2008
ACM
13 years 9 months ago
Exact combinational logic synthesis and non-standard circuit design
Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first ba...
Paul Tarau, Brenda Luderman
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 21 days ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
13 years 5 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
GECCO
2008
Springer
179views Optimization» more  GECCO 2008»
13 years 8 months ago
Developing neural structure of two agents that play checkers using cartesian genetic programming
A developmental model of neural network is presented and evaluated in the game of Checkers. The network is developed using cartesian genetic programs (CGP) as genotypes. Two agent...
Gul Muhammad Khan, Julian Francis Miller, David M....
CEC
2007
IEEE
13 years 9 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...