Sciweavers

2042 search results - page 402 / 409
» Automatic Understanding of Signals
Sort
View
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 23 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
14 years 22 days ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
SAC
2003
ACM
14 years 22 days ago
A Markov Random Field Model of Microarray Gridding
DNA microarray hybridisation is a popular high throughput technique in academic as well as industrial functional genomics research. In this paper we present a new approach to auto...
Mathias Katzer, Franz Kummert, Gerhard Sagerer
ISORC
2000
IEEE
13 years 12 months ago
Architecture, Design Methodology, and Component-Based Tools for a Real-Time Inspection System
We describe a real-time, component-based system for an inspection application. We chose the inspection application and the accompanying task (or scenario) so that we might fully e...
John Albert Horst
CAV
1998
Springer
175views Hardware» more  CAV 1998»
13 years 11 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore