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» Automatic Verification of Sequential Circuit Designs
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ICCAD
1998
IEEE
112views Hardware» more  ICCAD 1998»
13 years 11 months ago
Using precomputation in architecture and logic resynthesis
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
Soha Hassoun, Carl Ebeling
SIGSOFT
2007
ACM
14 years 7 months ago
Programming asynchronous layers with CLARITY
Asynchronous systems components are hard to write, hard to reason about, and (not coincidentally) hard to mechanically verify. In order to achieve high performance, asynchronous c...
Prakash Chandrasekaran, Christopher L. Conway, Jos...
TCAD
2010
121views more  TCAD 2010»
13 years 1 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
TASLP
2002
93views more  TASLP 2002»
13 years 6 months ago
Robust endpoint detection and energy normalization for real-time speech and speaker recognition
When automatic speech recognition (ASR) and speaker verification (SV) are applied in adverse acoustic environments, endpoint detection and energy normalization can be crucial to th...
Qi Li, Jinsong Zheng, A. Tsai, Qiru Zhou
DAC
2008
ACM
13 years 8 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik