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» Automatic Verification of Timed Circuits
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ECBS
2010
IEEE
209views Hardware» more  ECBS 2010»
14 years 3 months ago
Continuous Verification of Large Embedded Software Using SMT-Based Bounded Model Checking
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...
Lucas Cordeiro, Bernd Fischer 0002, João Ma...
AMAST
2006
Springer
14 years 2 months ago
State Space Representation for Verification of Open Systems
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...
Irem Aktug, Dilian Gurov
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
14 years 4 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
DAC
2010
ACM
13 years 9 months ago
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs
The verification of large radio-frequency/millimeter-wave (RF/MM) integrated circuits (ICs) has regained attention for high-performance designs beyond 90nm and 60GHz. The traditio...
Xuexin Liu, Hao Yu, Sheldon X.-D. Tan
DAC
2009
ACM
14 years 12 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke