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» Automatic Verification of Timed Circuits
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DAC
2009
ACM
14 years 12 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
FPL
2001
Springer
102views Hardware» more  FPL 2001»
14 years 3 months ago
A Generic Library for Adaptive Computing Environments
The Generic Library for Adaptive Computing Environments (GLACE) consists of a comprehensive set of module generators currently targeting Xilinx XC4000 and Virtex devices. In contra...
Tilman Neumann, Andreas Koch
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
14 years 3 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
14 years 4 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
TSE
2008
236views more  TSE 2008»
13 years 11 months ago
Provable Protection against Web Application Vulnerabilities Related to Session Data Dependencies
Web applications are widely adopted and their correct functioning is mission critical for many businesses. At the same time, Web applications tend to be error prone and implementat...
Lieven Desmet, Pierre Verbaeten, Wouter Joosen, Fr...