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IEEEPACT
2008
IEEE
14 years 2 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
WWW
2011
ACM
13 years 2 months ago
Counting triangles and the curse of the last reducer
The clustering coefficient of a node in a social network is a fundamental measure that quantifies how tightly-knit the community is around the node. Its computation can be reduce...
Siddharth Suri, Sergei Vassilvitskii
ISSAC
2007
Springer
128views Mathematics» more  ISSAC 2007»
14 years 1 months ago
Productivity and performance using partitioned global address space languages
Partitioned Global Address Space (PGAS) languages combine the programming convenience of shared memory with the locality and performance control of message passing. One such langu...
Katherine A. Yelick, Dan Bonachea, Wei-Yu Chen, Ph...
IPPS
2006
IEEE
14 years 1 months ago
Performance evaluation of wormhole routed network processor-memory interconnects
Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to ...
Taskin Koçak, Jacob Engel
ICPADS
2002
IEEE
14 years 17 days ago
Hardware-based IP Routing Lookup with Incremental Update
Nowadays, the commonly used table lookup scheme for IP routing is based on the so-called classless interdomain routing (CIDR). With CIDR, routers must find out the best matching ...
Pi-Chung Wang, Chia-Tai Chan, Shuo-Cheng Hu, Yu-Ch...