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VLSI
2005
Springer
14 years 1 months ago
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
Erik Larsson, Stina Edbom
KBSE
2005
IEEE
14 years 1 months ago
Automated test generation for engineering applications
In test generation based on model-checking, white-box test criteria are represented as trap conditions written in a temporal logic. A model checker is used to refute trap conditio...
Songtao Xia, Ben Di Vito, César Muño...
DAC
1997
ACM
14 years 1 hour ago
Frequency-Domain Compatibility in Digital Filter BIST
We examine frequency-domain issues in the design and selection of on-chip test generators for built-in self-test (BIST) of highperformance digital filters. Test-generator/circuit...
Laurence Goodby, Alex Orailoglu
TOOLS
2010
IEEE
14 years 27 days ago
Contract-Driven Testing of JavaScript Code
JSContest is a tool that enhances JavaScript with simple, type-like contracts and provides a framework for monitoring and guided random testing of programs against these contracts ...
Phillip Heidegger, Peter Thiemann
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...