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CODES
2010
IEEE
13 years 4 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem
NAR
2008
125views more  NAR 2008»
13 years 7 months ago
Phylogeny.fr: robust phylogenetic analysis for the non-specialist
Phylogenetic analyses are central to many research areas in biology and typically involve the identification of homologous sequences, their multiple alignment, the phylogenetic re...
Alexis Dereeper, V. Guignon, G. Blanc, Stép...
HPCA
2009
IEEE
14 years 7 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
CAISE
2008
Springer
13 years 9 months ago
An Electronic Market-place Centralising Exchanges in the Virtual Enterprise: a Model Proposition
In this paper, we show that Service Oriented Architectures enable exchanges to be more flexible inside the virtual enterprise (VE), because they create an electronic market-place b...
Hervé Mathieu
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
13 years 10 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...