Automatic memory partitioning: increasing memory parallelism via data structure partitioning

In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the performance of accelerated applications. Currently, programmers must manually assign data structures to specific memory banks on the accelerator. This paper presents Automatic Memory Partitioning, a method for automatically partitioning data structures into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. Experiments show significant improvements in performance while using a minimal number of memory banks. Categories and Subject Descriptors B.5.2 [Automatic synthesis] General Terms Performance, Design Keywords Memory, Parallelism, FPGA

• Type: Journal
• Year: 2010
• Where: CODES
• Authors: Yosi Ben-Asher, Nadav Rotem
• Keywords: CODES 2010, Data Structures, Memory Banks, Multiple Memory Banks, Software Engineering